1. Field of the Invention
The invention relates to a method of detecting binary information from an output signal of a charge transfer device, which signal comprises a train of pulses, which device is used for temporarily storing or for delaying said binary information in the form of charge packets, the amplitude of said pulses being representative of the binary information and being compared, in a comparator circuit, with a reference signal derived from an output signal of a reference source.
The invention also relates to a device for carrying out the method in accordance with the invention.
2. Description of the Prior Art
A known such method is utilized in existing circuit arrangements, for example the Texas Instruments TMS 364 described on pages 221-225 of the book "Charge Coupled Devices and Systems" by the authors Howes, M.J. and Morgan, D.V. (Published by Wiley & Sons 1979). In accordance with the known method the comparator circuit determines whether the output signal of the charge transfer device is larger or smaller than the reference signal. In the first-mentioned case, for example, a logic "1" will be detected, while in the last-mentioned case this will be a "0".
As is known, charge transfer devices comprise an array of cells arranged in sequence, between which charge transfer is possible under the influence of suitable clock signals. It is also known that such charge transfer devices have the disadvantage that, during transfer of a charge packet from one cell to the following cell, a residual charge is left in the first-mentioned cell, so that, firstly, the charge packet being transferred decreases in magnitude and, secondly, the residual charge is added to the next charge packet. For example, when a charge transfer device is used as a digital shift register, a charge packet representing a logic "0" may be distorted by a charge packet which represents a logic "1" and which directly precedes the first-mentioned charge packet. When the known method is used it may happen that the second charge packet is distorted to such an extent that a logic "1" is detected erroneously. It is obvious that a similar error may occur in the case of a logic "1" which follows a logic "0".